EUV Lithography Process Explained: The Physics and Engineering of Sub-7nm Chips

EUV Lithography Process Explained: The Physics and Engineering of Sub-7nm Chips

EUV Lithography Process Explained: The Physics and Engineering of Sub-7nm Chips

By Alex Morgan
Senior Technology Analyst | Covering Enterprise IT, AI & Emerging Trends

Introduction to Extreme Ultraviolet (EUV) Lithography

For decades, the semiconductor industry utilized Deep Ultraviolet (DUV) light to etch circuits onto silicon wafers. As the industry approached the physical limits of Moore’s Law, the 193-nanometer wavelength of DUV became a resolution bottleneck. To continue scaling transistors to the 7nm, 5nm, and 3nm nodes, the industry transitioned to Extreme Ultraviolet (EUV) lithography. This technology has become a critical component of modern semiconductor manufacturing.

EUV lithography utilizes a wavelength of 13.5 nanometers, which is significantly shorter than the 193nm wavelength used in DUV. This allows for the patterning of smaller and more densely packed features. The transition to EUV required a complete redesign of photolithography systems, including the implementation of high-vacuum environments, specialized reflective optics, and new methods for light generation.

The Physics of 13.5 Nanometers

The selection of 13.5 nm as the standard for EUV was determined by the availability of multilayer reflective coatings. Because EUV radiation is absorbed by nearly all matter, including air and traditional refractive glass lenses, the lithography process must occur within a high vacuum. Furthermore, the system must utilize specialized mirrors instead of traditional lenses to direct the light.

The sensitivity of EUV to absorption presents significant engineering challenges. Gas molecules within the chamber can attenuate the beam, and contamination on optical surfaces can result in patterning defects. Consequently, EUV systems require stringent environmental controls and maintenance protocols.

The EUV Light Source: Laser-Produced Plasma

EUV machines generate light using a method known as Laser-Produced Plasma (LPP). In a standard ASML TWINSCAN NXE system, a generator releases 50,000 droplets of molten tin per second. Each droplet, approximately 30 microns in diameter, is struck by a high-power CO2 laser in two stages.

The first pulse reshapes the droplet, and the second pulse vaporizes it into a plasma. This plasma reaches temperatures of nearly 500,000 degrees Celsius, emitting 13.5 nm EUV photons. This light is then collected by a parabolic mirror and directed into the illumination system for patterning.

Reflective Optics and Bragg Reflectors

Because glass absorbs EUV light, the process relies on Bragg reflectors. These mirrors consist of approximately 40 to 50 alternating layers of molybdenum and silicon. Each layer is precisely deposited to utilize constructive interference to reflect EUV light.

Current mirror technology achieves approximately 70% reflectivity, with the remaining 30% of energy absorbed as heat. Because the light undergoes multiple reflections before reaching the wafer, high source power is required to ensure sufficient light intensity for the exposure process.

The Photomask and the Pellicle

In EUV lithography, the photomask must be reflective. It is constructed from a multi-layer substrate similar to the system mirrors, with a light-absorbing material defining the circuit pattern. To protect the mask from particulate contamination, manufacturers use a pellicle—a thin, transparent membrane.

Developing pellicles that are both durable and transparent to EUV light is a significant area of material science. Leading manufacturers like TSMC and Samsung utilize advanced materials, such as polysilicon or carbon nanotubes, to maintain high yields in 5nm and 3nm production lines.

Integration in Advanced Semiconductor Manufacturing

The implementation of EUV has streamlined the semiconductor fabrication workflow. To achieve 7nm-class features with DUV, manufacturers often relied on multi-patterning, which requires multiple exposures for a single layer. EUV allows for single-patterning of many complex layers, reducing the number of mask layers required and minimizing potential overlay errors. This efficiency is essential for the production of high-performance computing (HPC) and mobile processors.

Industry Applications: Apple and NVIDIA

EUV lithography is currently utilized in high-volume manufacturing for consumer electronics. Apple’s A-series and M-series chips, produced by TSMC, were among the first to utilize EUV at scale. The A15 Bionic chip, for example, contains approximately 15 billion transistors, a density enabled by EUV precision.

NVIDIA’s Hopper and Blackwell GPU architectures also utilize EUV to achieve the transistor density and interconnect speeds required for artificial intelligence and data center applications. The resolution provided by 13.5 nm light is a primary factor in maintaining the power efficiency of these large-scale dies.

The Future: High-NA EUV

As the industry moves toward the 2nm node and beyond, manufacturers are transitioning to High Numerical Aperture (High-NA) EUV. The ASML EXE series features a numerical aperture of 0.55, compared to the 0.33 NA of current systems. This increase in NA allows for even higher resolution patterning.

High-NA EUV systems require larger footprints and redesigned optics. Intel has begun taking delivery of the first High-NA systems to support its future process technology roadmap. This evolution indicates that EUV will remain the foundational technology for semiconductor manufacturing for the foreseeable future.

Conclusion

EUV lithography is a sophisticated manufacturing technique that enables the continued scaling of integrated circuits. By utilizing plasma-generated light and atomic-scale reflective optics, it supports the advancement of global computing infrastructure. While the capital expenditure for a single machine can exceed $150 million, the technology is essential for the production of next-generation semiconductors.

Sources

  • ASML Holding N.V. - "EUV Technology Overview and Future Roadmap"
  • IEEE Spectrum - "The Physics of EUV Lithography"
  • TSMC Technical Documentation - "5nm and 3nm Process Node Advancements"
  • Intel Corporation - "High-NA EUV Implementation"
  • Semiconductor Engineering - "EUV Pellicle and Mask Technology"

This article was AI-assisted and reviewed for factual integrity.

Photo by Adam Winger on Unsplash