The 2D Material Mirage: Quantifying Schottky Barrier Variability in MoS2 and WS2 Gate Stacks

By Rizowan Ahmed (@riz1raj)
Senior Technology Analyst | Covering Enterprise IT, Hardware & Emerging Trends

The semiconductor industry’s exploration of 2D materials faces significant thermodynamic challenges. While Transition Metal Dichalcogenides (TMDCs) have been identified as potential candidates for extending Moore’s Law, integration into the fabrication process reveals complex physical hurdles. The industry is currently addressing the physics of the interface, specifically the Schottky barrier height (SBH) variability in CVD-grown monolayer MoS2 and WS2 transistors, which remains a primary concern for 2nm Gate-All-Around FET (GAAFET) performance.

The Interfacial Challenge: Theory and Contact Realities

In ideal conditions, the Schottky-Mott rule describes the relationship between metal work functions and semiconductor electron affinity. However, in advanced logic stacks, this relationship is often disrupted by Fermi Level Pinning (FLP). This phenomenon occurs when the metal-semiconductor interface is influenced by Metal-Induced Gap States (MIGS) and defect-induced states. Research into Interfacial Resistance in 2nm GAAFETs suggests that the Van der Waals gap is frequently affected by sulfur vacancies and chemical residues from the growth and transfer processes.

SBH Variability: MoS2 vs. WS2

When comparing Chemical Vapor Deposition (CVD) grown MoS2 and WS2, variability in SBH presents a significant integration challenge. Analysis of current wafer-scale growth reveals several technical realities:

• MoS2 SBH Distribution: Variability is often attributed to a high density of sulfur vacancies ($V_s$), which act as n-type dopants and pin the Fermi level near the conduction band edge.
• WS2 SBH Distribution: While WS2 theoretically offers high hole mobility, its empirical SBH variability is a known hurdle. Factors such as spin-orbit coupling and orbital hybridization at the contact lead to varying behavior depending on the metal deposition protocol utilized.
• Contact Resistance ($R_c$): Achieving low $R_c$ in TMDC stacks remains a primary objective, as current configurations often exceed the requirements for high-performance logic compared to traditional silicon-based nodes.

The CVD Growth Process: Structural Considerations

The transition to large-area CVD growth is essential for commercialization but introduces variables that affect Schottky barrier height control. CVD-grown monolayers are typically polycrystalline. The grain boundaries (GBs) in these films can act as scattering centers and sites for impurity segregation.

In MoS2, these grain boundaries can result in local variations in potential, leading to spatially inhomogeneous SBH. In a scaled channel, the presence of grain boundaries can significantly influence device characteristics. WS2, despite advancements in MOCVD (Metal-Organic CVD) processes, is susceptible to strain-induced bandgap modulation. Thermal mismatch between the growth substrate and the WS2 film creates residual strain that shifts the band edges, complicating SBH uniformity.

The Logic Gate Stack: Integration Analysis

Integration of TMDCs into 2nm GAAFET architectures faces difficulties during the High-k/Metal Gate (HKMG) sequence. Unlike traditional Silicon or SiGe flows, the deposition of the dielectric via Atomic Layer Deposition (ALD) can impact the underlying 2D lattice.

Key Integration Challenges:

• Oxygen Interaction: During ALD, oxygen precursors may react with the TMDC surface, potentially creating sub-oxides that increase interfacial layer thickness and affect Equivalent Oxide Thickness (EOT) scaling.
• Orbital Overlap: The lack of dangling bonds on the TMDC surface can limit covalent bonding with the gate dielectric, contributing to interface state density ($D_{it}$).
• Thermal Budget: The annealing processes required for dielectric quality or dopant activation must be carefully managed to avoid degrading the TMDC-metal contact or causing unwanted diffusion.

MoS2: Current Implementation Path

The industry currently utilizes MoS2 for n-type logic research because its pinning characteristics are relatively well-documented. The SBH variability in MoS2 is being addressed using semi-metal contacts such as Bismuth (Bi) or Antimony (Sb), which aim to minimize MIGS through a 'cold metal' contact strategy. However, the integration of these metals must be balanced with standard CMOS back-end-of-line (BEOL) thermal requirements.

WS2: Performance Potential and Hurdles

WS2 is a candidate for p-type TMDC logic due to its hole effective mass characteristics. However, interfacial resistance in WS2 transistors remains higher than established silicon equivalents. The SBH for WS2 is sensitive to the contact metal's work function, but FLP often prevents the expected p-type contact even when using high-work-function metals like Pt or Pd, sometimes resulting in high-resistance ambipolar behavior.

The Outlook for Advanced Nodes

The development of TMDC-based logic continues to evolve. Current industry trends suggest a focus on hybrid integration strategies. This may involve utilizing TMDCs for specific power-management or RF functions alongside traditional silicon architectures.

Addressing SBH variability through methods such as remote plasma doping or monolayer-compatible ALD precursors is essential for the viability of TMDCs in primary conduction channels. While 'Transfer-Free' growth directly on wafers is being explored to reduce contamination, managing grain boundary issues remains critical. The industry continues to evaluate stacked nanosheet Silicon and complementary FETs (CFETs) as the primary path for upcoming nodes while 2D materials undergo further refinement.

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